View source for Socket G3 Memory Extender

The '''Socket G3 Memory Extender''' ('''G3MX''') was a planned [[Advanced Micro Devices]]' solution to the problem of connecting large amounts of memory to a single microprocessor. The G3MX was expected to be available on [[AMD 800 chipset series|AMD 800S series chipset]] for server market starting from 2009, but was officially cancelled together with the cancellation of [[AMD Socket G3|Socket G3]] in early 2008.<ref>{{in lang|ja}} [http://pc.watch.impress.co.jp/docs/2008/0520/kaigai440.htm PC Watch report], retrieved August 20, 2008</ref>

Electrical limitations preclude connecting more than 2 unbuffered [[DDR SDRAM]] [[DIMM]]s or 4 buffered DIMMs to a single shared bus. It is also impractical to manufacture a single chip with more than two DDR memory buses (channels). Thus, it is impossible to connect more than 8 DIMMs to a single chip. This is typically the per-processor limitation as well.

The obvious solution is to use a narrower, higher-speed bus to interface to memory, and to implement it as a [[point-to-point (telecommunications)|point-to-point]] link, [[Daisy chain (electrical engineering)|daisy-chaining]] additional modules. However, [[Intel]] have made two attempts at this, neither hugely successful:

* [[RDRAM]] implements the bus on a DRAM chip. However, the high-speed circuitry increased power consumption, and the daisy-chaining caused significantly higher [[memory latency]].  Because it is difficult to implement high-speed circuitry on the same [[semiconductor device fabrication|semiconductor process]], costs were high.
* [[FB-DIMM]]s add a separate memory controller chip to each memory DIMM. This "advanced memory buffer" (also known by the abbreviation ''AMB'') provides the necessary high-speed circuitry.  However, the same power and heat problems have arisen.

AMD's answer to this is the G3MX chip. This is very similar to the AMB, but is intended to be placed on the [[motherboard]], not on the DIMM. It can connect to multiple DIMMs but, to minimize latency, is not designed to be daisy-chained.

The G3MX has an asymmetrical link to the processor, to match typical memory usage patterns.  20 differential signals supply read data to the processor, and 13 differential signals receive commands and write data. This totals 66 pins, less than half of what is required for a DDR2 or DDR3 interface. Thus, a processor can easily have 4 G3MX memory interfaces, each with 4 buffered DIMMs attached, allowing up to 16 DIMMs to feed one processor.

== References ==
* {{cite press release |url=https://www.amd.com/us-en/Corporate/VirtualPressRoom/0%2c%2c51_104_543~118446%2c00.html |title=AMD Unveils Forward-Looking Technology Innovation To Extend Memory Footprint for Server Computing |publisher=Advanced Micro Devices |date=2007-07-25 |accessdate=2007-10-07}}
* {{cite web |url=http://www.vnunet.com/vnunet/news/2194881/amd-unveils-memory-system |title=AMD claims memory controller breakthrough |author=Shaun Nichols |location=California |publisher=vnunet.com |date=2007-07-25 |accessdate=2007-10-07}}
* {{cite web |url=http://www.hothardware.com/News/More_AMD_G3MX_Details_Emerge/ |title=More AMD G3MX Details Emerge |author=Marco Chiappetta |date=2007-08-22 |publisher=HotHardware |accessdate=2007-10-07}}  Also mentions rumors that Intel is working on a similar on-motherboard "AMB2".
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[[Category:AMD products]]
[[Category:X86 memory management]]