File:Carry-select-adder-variable-size.png
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| Description |
This is a diagram of a 16-bit carry select adder with chunk sizes 2-2-3-4-5. The lowest 2 bits do not need the muxing structure since its carry is already known. This break-up assumes that a mux delay is approximate to that of a full adder delay (which is very unlikely). |
|---|---|
| Source |
Own work |
| Date |
12 April 2009 |
| Author |
Quanticles (talk) (Uploads) |
| Permission (Reusing this file) |
See below.
|
Summary
This is a diagram of a 16-bit carry select adder with chunk sizes 2-2-3-4-5. The lowest 2 bits do not need the muxing structure since its carry is already known. This break-up assumes that a mux delay is approximate to that of a full adder delay (which is very unlikely).
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