File:MIPS Architecture (Pipelined).svg
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Summary
| Description |
English: The stage-by-stage architecture of a MIPS microprocessor with a pipeline. Although the memory is shown twice for clarity of the pipeline, MIPS architectures have only one memory bank (i.e. von Neumann architecture). |
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| Date | |||
| Source | Own work | ||
| Author | Inductiveload | ||
| Permission (Reusing this file) |
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| Other versions | rkrkgkf | ||
| SVG development |   This file uses translateable embedded text. |
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 18:08, 22 January 2009 | | 800 × 500 (56 KB) | wikimediacommons>Inductiveload | {{Information |Description={{en|1=The stage-by-stage architecture of a MIPS microprocessor with a pipeline. Although the memory is shown twice for clarity of the pipeline, MIPS architectures have only one memory bank (i.e. von Neumann architecture).}} |So |
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